Cadence and GLOBALFOUNDRIES Collaborate to Improve DFM Signing at 20 and 14nm Nodes

Cadence Design Systems, the global leader in electronic design innovation, recently announced that GLOBALFOUNDRIES has teamed up with Cadence® to provide pattern classification data for its 20- and 14-nanometer processes. GLOBALFOUNDRIES adopts Cadence pattern classification and pattern matching solutions because they can speed up DFM by four times, which is critical to increase customer wafer yield and predictability.

"We have integrated the Cadence pattern classification technology to divide the unfavorable yield factors into several pattern groups based on pattern similarity, including inaccurate patterns, thereby increasing the efficiency of DRC+, a pattern-based lithography sign-off process." GLOBALFOUNDRIES DFM Partnership Luigi Capodieci, person and senior director, said. “The innovative DRC+ sign-off process has been successfully applied to a variety of 32- and 28-nanometer production IC designs. Now, we use it for the most advanced process sizes available.”

The Cadence pattern classification technology allows GLOBALFOUNDRIES to classify hundreds of thousands of yield failures, process hotspots, and wafer failures as an easy-to-use model library. Cadence pattern search and match analysis are embedded in Cadence lithography physics analyzers, physical verification systems, unified Virtuoso® custom/analog and Encounter® digital implementation system solutions. This gives GLOBALFOUNDRIES's customers the flexibility to use Encounter and Virtuoso's signature matching and automatic repair in the design, establish a one-hundredth correspondence with the full-chip sign-off process, and has been successfully applied to several advanced node mass production chip.

For GLOBALFOUNDRIES customers using Cadence design tools, this silicon-proven DFM process is easy to use and integrates seamlessly with Cadence's custom, digital, and full-chip sign-off processes. The pattern-matching DRC+ is integrated into the Virtuoso layout suite to achieve a robust, well-designed approach and achieves fine-grained avoidance and automatic repair of bad patterns. The Encounter Digital Implementation System has been able to accurately and quickly find and fix 100% of DRC+ violations without introducing additional DRC or DRC+ violations and has been successfully applied to several 28nm designs.

"DFM serves as an increasingly important link between chip development and manufacturing, and can play a major role in wafer yield and predictability," said Xu Jiping, senior vice president of Cadence chip implementation group. "The Cadence pattern classification technology helps GLOBALFOUNDRIES customers set and achieve high yield expectations, ensuring they receive the highest possible returns from complex designs. GLOBALFOUNDRIES promises to use our technology at 20, 14 nm and subsequent process nodes. We Thanks for this."